1. Field
Exemplary embodiments of the present invention relate to a memory device.
2. Description of the Related Art
FIG. 1 is a diagram illustrating part of a conventional memory device 100.
Referring to FIG. 1, the memory device may include first and second banks 110 and 120, first and second sense amplifier groups 130 and 140, first and second local buses LIO1<0:7>/LIO1B<0:7> and LIO02<0:7>/LIO2B<0:7>, and first and second input/output buses IO1<0:7> and IO2<0:7>.
In the memory device 100 of FIG. 1, each of the first and second banks 110 and 120 may include a plurality of memory cells (not shown in FIG. 1) for storing data.
The first and the second local buses LIO1<0:7>/LIO1B<0:7> and LIO2<0:7>/LIO2B<0:7> may transfer data, output by the first and the second banks 110 and 120, to the first and the second sense amplifier groups 130 and 140, respectively. For reference, the data output by the first and second banks 110 and 120 includes data in which data of 1 bit includes primary data and secondary data using differential signaling (hereinafter called differential data). Accordingly, the first and second local buses LIO1<0:7>/LIO1B<0:7> and LIO2<0:7>/LIO2B<0:7> may include the plurality of primary local lines LIO1<0:7> and IO2<0:7> for transferring the primary data and the plurality of secondary local lines LIO1B<0:7> and LIO2B<0:7> for transferring the secondary data.
Each of the first and second sense amplifier groups 130 and 140 may include a plurality of input/output sense amplifiers (not shown in FIG. 1) for amplifying the data of each of the local buses LIO1<0:7>/LIO1B<0:7> and LIO2<0:7>/LIO2B<0:7> and outputting the amplified data. For reference, the first and second sense amplifier groups 130 and 140 may convert differential data into data using single ended signaling (hereinafter called single data) and output the converted data.
The first and second input/output buses IO1<0:7> and IO2<0:7> may transfer data output by the respective sense amplifier groups 130 and 140.
In a read operation, when the first bank 110 is selected, data output by the first bank 110 may be transferred to the first sense amplifier group 130 through the first local buses LIO1<0:7>/LIO1B<0:7>, may be amplified, and may be transferred through the first input/output buses IO1<0:7>. Furthermore, in a read operation, when the second bank 120 is selected, data output by the second bank 120 may be transferred to the second sense amplifier group 140 through the second local buses LIO2<0:7>/LIO2B<0:7>, may be amplified, and may be transferred through the second input/output buses IO2<0:7>.
In the memory device 100 of FIG. 1, the first and second banks 110 and 120 include independent data output paths. Accordingly, an operation for reading the data of the first and second banks 110 and 120 can be performed without being limited to a CAS (column access strobe) to CAS delay time (tCCD). For example, the data of the second bank 120 may be read while the data of the first bank 110 is read. However, the area of the memory device 100 may be greatly increased because each bank needs to include local buses, a sense amplifier group, and input/output buses.
FIG. 2 is a diagram illustrating part of another conventional memory device 200.
Referring to FIG. 2, the memory device 200 may include first and second banks 210 and 220, first and second switch groups 230 and 240, a sense amplifier group 250, and first and second local buses LIO1<0:7>/LIO1B<0:7> and LIO2<0:7>/LIO2B<0:7>, and input/output buses IO<0:7>.
When the first bank 210 is selected, the first switch group 230 couples the first local buses LIO1<0:7>/LIO1B<0:7> and the sense amplifier group 250. When the second bank 220 is selected, the second switch group 240 couples the second local buses LIO2<0:7>/LIO2B<0:7> and the sense amplifier group 250. Each of the first and second switch groups 230 and 240 may include a plurality of switches (not shown in FIG. 2) coupled between the local lines and sense amplifiers.
The sense amplifier group 250 may include a plurality of input/output sense amplifiers (not shown in FIG. 2) for amplifying the data of local buses corresponding to a selected bank and outputting the amplified data. The input/output buses IO<0:7> may transfer data outputted by the sense amplifier group 250.
In a read operation, when the first bank 210 is selected, the first switch group 230 couples the first local buses LIO1<0:7>/LIO1B<0:7> and the sense amplifier group 250. Data output by the first bank 210 may be transferred to the sense amplifier group 250 through the first local buses LIO1<0:7>/LIO1B<0:7>, may be amplified, and may be transferred through the input/output buses IO<0:7>.
Furthermore, in a read operation, when the second bank 220 is selected, the second switch group 240 couples the second local buses LIO2<0:7>/LIO2B<0:7> and the sense amplifier group 250. Accordingly, data output by the second bank 220 may be transferred to the sense amplifier group 250 through the second local buses LIO2<0:7>/LIO2B<0:7>, may be amplified, and may be transferred through the input/output buses IO<0:7>.
The area of the memory device 200 can be reduced because the first and second banks 210 and 220 share the data output path. However, the data of the first and second banks 210 and 220 cannot be read at the same time, and there is a specific temporal restriction when data is continuously read. That is, when one of the first and second banks 210 and 220 is read, the data of the other of the first and second banks 210 and 220 cannot not be read within a specific time after the data of the one of the first and second banks 210 and 220 is read.
Typically, switches included in the first and second switch groups 230 and 240 are pass gates which generally have a high turn-on resistance. Accordingly, a high-speed operation of a memory device may be disadvantageous due to a delay generated when the data of local buses passes through the pass gate.